Semiconductor memory devices, and particularly Dynamic Random Access Memory (DRAM) devices are well known. An essential feature of a DRAM is a memory cell. A cell comprises a capacitor for storing charge and an access transistor (also referred to as a pass transistor or a pass gate) for transferring charge to and from the capacitor. Trench, or deep trench (DT), capacitors are typical and are well known. A cell also comprises a means (often referred to as a strap) for connecting one transistor source/drain region to the capacitor. At the present state of the art, more than 256 million DRAM cells are present on a memory chip, organized in the form of an array. Thus, because cell size determines chip density, size and cost, reducing cell area is the DRAM designer's primary goal. Cell area may be reduced by shrinking the individual feature size, or by forming structures which make more efficient use of the chip surface area. The latter approach is particularly desirable.
In a typical process for fabricating DRAM devices having trench capacitors, the capacitor structure is completely formed prior to the formation of the transistor gate conductor (GC) structure. Thus, a typical process sequence involves the steps of opening the trench, filling the trench, forming the node conductors, then forming the gate stack structure.
As is known in the art, integrated circuits (ICs) or chips employ capacitors for charge storage purposes. An example of an IC that employs capacitors for storing charge is a memory IC, such as a dynamic random access memory (DRAM) chip. The level of the charge (“0” or “1”) in the capacitor represents a bit of data.
A DRAM chip includes an array of memory cells interconnected by rows and columns. Typically, the row and column connections are referred to as wordlines and bitlines, respectively. Reading data from or writing data to the memory cells is accomplished by activating the appropriate wordlines and bitlines.
Typically, a DRAM memory cell comprises a transistor connected to a capacitor. The transistor includes two diffusion regions separated by a channel, opposite which is located a gate. Depending on the direction of current flow between the diffusion region, one is referred to as the drain and the other the source. The terms “drain” and “source” are herein used interchangeably to refer to the diffusion regions. The gate is coupled to a wordline and one of the diffusion regions is coupled to a bitline. The other diffusion region is coupled to the capacitor. Applying an appropriate voltage to the gate switches the transistor on, enabling current to flow through channel between the diffusion regions to form a connection between the capacitor and bitline. Switching off the transistor severs this connection by preventing current flowing through the channel.
The charge stored in the capacitor dissipates over time due to current leakage therefrom. Before the charge dissipates to an indeterminate level (below a threshold), the node has to be refreshed.
Continued demand to shrink devices has facilitated the design of DRAMs having greater density and smaller feature size and cell area. To produce cells that occupy less surface area, smaller components such as capacitors are used. However, the use of smaller capacitors results in decreased storage capacity, which can adversely affect the performance and operability of the memory device. For example, sense amplifiers require an adequate signal level to reliably sense the information in the cells. The ratio of storage capacitance to bitline capacitance is crucial in determining the signal level. If the capacitor becomes too small, this ratio may be too small to provide an adequate signal. Also, smaller storage capacity requires higher refresh frequency.
One type of capacitor that is commonly employed in DRAMs is a trench capacitor. A trench capacitor is a three-dimensional structure formed in the silicon substrate. Increasing the volume or capacitance of the trench capacitor can be achieved by etching deeper into the substrate. As such, increasing the capacitance of the trench capacitor does not increase the surface area of the cell.
A conventional trench capacitor comprises a trench etched into the substrate. The trench is typically filled with n+ doped poly which serves as an electrode of the capacitor (referred to as the storage node). Optionally, a second electrode of the capacitor, referred to as a “buried plate,” is formed by out-diffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A n+ doped silicate glass such as Arsenic doped silicate glass (ASG) serves as the dopant source. A node dielectric comprising nitride is provided to separate the two electrodes of the capacitor.
In the upper portion of the trench, a dielectric collar is provided to prevent leakage from the node junction to the buried plate. The node dielectric in the upper portion of the trench where the collar is to be formed is removed prior to its formation. Removal of the nitride prevents vertical leakage along the collar.
There is constant pressure to reduce the dimensions of DRAM cells and constant pressure to save cost by reducing the depth of the trench.
Planar capacitors use two or more capacitor storage plates in the same silicon area.
Trench capacitor technology has not been able to place two or more storage palates in a trench.